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[VHDL-FPGA-Verilog] RS232_COMPLETE

Description: Communication RS232 between Hyperterminal PC to FPGA Spartan 3E
Platform: | Size: 472064 | Author: MarceloBG | Hits:

[Other Embeded program] MyC2Board_RS232_Test

Description: 这是一个Altera FPGA NIOS II RS232通讯程序。 在Quartus II工程中，用Qsys建立了一个NIOS II为核心的CPU系统，并挂接了一个RS232接口。 在software目录下，有三个工程，一个是用C++类包装的RS232类的Eclipse工程，一个是不用C++类包装的Eclipse工程，还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上，与FPGA中的NIOS II通讯。 这个实验的主要目的是编写一个通用RS232类，这个类即可以用于NIOS II，又可以用于PC机，是一个可重用的RS232类；我们用这个类开发了不少以PC为控制平台，FPGA为硬件控制器的测试系统。 -This is an Altera FPGA NIOS II RS232 communication project. In the Quartus II project, there is a NIOS II CPU with RS232. In the Software directory, there are 3 projects. First one is an Eclipse Project with C++ RS232 Class. Second one is an Eclipse Project with C RS232.h. Other one is a VC++2008 Project with C++ RS232 Class. The purpose of this project is to write a RS232 Class use on any system needed RS232 communication. The RS232 Class not only use on NIOS II, but also use on PC. We used this RS232 Class on many Test Systems with PC and FPGA
Platform: | Size: 13864960 | Author: li hui xian | Hits:

[VHDL-FPGA-Verilog] test_uart

Description: 基于FPGA的串口通信实验,能将PC发给FPGA的信息原样返回给PC机-FPGA-based serial communication experiment, the information sent to the FPGA can PC as it returns to the PC
Platform: | Size: 492544 | Author: 猫子 | Hits:

[ARM-PowerPC-ColdFire-MIPS] GNSS_OEM_USB_FPGA

Description: fpga usb 采集程序，将AD采集过来的数据经USB传给PC机-fpga usb acquisition program, the AD acquisition over the data passed to the PC via USB
Platform: | Size: 35840 | Author: wangpoba | Hits:

[Windows Develop] FEP1C3_12_7_SP

Description: 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。 已通过测试。 -FPGA-based signal acquisition and spectrum analysis, using VHDL prepared compression bag Quartus engineering. AD sampling using the state machine to achieve now, and into the LPM_RAM. Design a UART module (which is also the state machine), the data is sent to the PC. Has passed the test.
Platform: | Size: 215040 | Author: l2003l | Hits:

[VHDL-FPGA-Verilog] FPGA_RS232

Description: FPGA芯片,利用Verilog硬件描述语言实现与PC电脑通信功能。-FPGA chip, the Verilog hardware description language and PC computer communication function.
Platform: | Size: 514048 | Author: tanyu | Hits:

[Com Port] clk_test

Description: UART串口程序，将FPGA数据传到上位机上-UART program,transmitting data from FPGA to PC
Platform: | Size: 5120 | Author: | Hits:

[Other] uart2

Description: PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示-PC, open the serial debugging assistant to send a character to the development board (the middle through the serial line connected) FPGA received after the character, and posted back to the PC, assistant serial
Platform: | Size: 625664 | Author: wuwanzheng | Hits:

[assembly language] UART_RS232(verilog)

Description: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
Platform: | Size: 600064 | Author: 饕餮小宇 | Hits:

[assembly language] UART_RS232(VHDL)

Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
Platform: | Size: 607232 | Author: 饕餮小宇 | Hits:

[SCM] USB11_ACEX1K

Description: FPGA文件负责采集传感器数据，然后传给51单片机，51单片机通过usb将信号传递给上位机，，vc文件是上位机软件界面，-FPGA file is responsible for collecting sensor data, and then passed to the 51 single-chip, 51 single-chip signal transmitted to the host computer via usb vc file is a PC software interface
Platform: | Size: 13870080 | Author: dasf | Hits:

[VHDL-FPGA-Verilog] jieshoufasong

Description: 实现FPGA和PC机之间的通信。PC机发送的数据可以通过FPGA显示在数码管上；FPGA通过按键发送的数据可以显示在PC机的串口调试助手上。-Communication between the FPGA and the PC. PC sends the data can be displayed through the FPGA digital tube FPGA through the button to send the data can be displayed on a PC serial port debugging assistant.
Platform: | Size: 706560 | Author: xiaotian | Hits:

[VHDL-FPGA-Verilog] I2C_400K

Description: 通过I2C接口实现FPGA和PC通信的Verilog源代码，测试条件400KHz，I2C接口内部集成了寄存器。-The Verilog FPGA and PC communications through the I2C interface source code, test conditions 400KHz I2C interface internal integration register.
Platform: | Size: 128000 | Author: 曹操 | Hits:

[VHDL-FPGA-Verilog] nano-logic

Description: 本手册适用于使用NANO-LOGIC CPLD 系列开发板的用户。 一款较高端FPGA 开发板既可以做项目开发也可以配上一个“通用的基础设备接口 板”作为新人培训入门使用 本产品的推出旨在于方便用户扩展基础设备和初学者学习使用。在FPGA 产品的设计 中，在初期调试时为了方便调试和显示程序工作状态，经常会用到大量的调试接口，比 如灯、按键、液晶显示等设备；这些设备既浪费有限的FPGA 资源又浪费宝贵的板卡体 积。本开发板提供了通常用户调试程序所需要的基础输入输出和上位机通讯接口，仅用 了6 个用户IO，扩展了相当于40 多个IO 的用户基础设备。这些用户基础设备可以并行 使用互不干扰。此开发板可以和本公司所用FPGA 产品配合使用，同时本开发板采用了 通用的2.54mm 连接器方便了用户与自己的FPGA 产品进行连接。-This manual applies to the use the NANO-LOGIC CPLD series development board user. A higher-end FPGA development board can do both project development can also be coupled with a common basis for device interface board as a new training started to use the product launch aimed at expansion of infrastructure and user-friendly for beginners to learn to use. To facilitate debugging and display program work state in the early debugging FPGA design often use a lot of debug interface devices such as lights, buttons, LCD these devices not only a waste of limited FPGA resources and waste valuable board volume. The development board provides the usual user debugger need basic input and output, and PC communication interface, only six user IO, and expansion of the user base is equivalent to more than 40 IO devices. User base device can be used in parallel without disturbing each other. This development board can be used by the Company with the use of FPGA products, at the same time, the developmen
Platform: | Size: 737280 | Author: 王培明 | Hits:

[source in ebook] rs232

Description: fpga与pc机的rs232的通信代码，简单全面-the fpga with pc rs232 communication code, simple and comprehensive
Platform: | Size: 5120 | Author: funi | Hits:

[Com Port] UART_VHDLCodes

Description: 基于VHDL的异步串口收发器，在FPGA上设计Uart接收模块实现从pc接收串口数据； 在FPGA上设计Uart发送模块，把从pc接收的数据的16进制值加1再发送给PC； 设计单片机和FPGA接口模块，把接收到的数据送给单片机，并显示在LCD上 -VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data design the Uart send module on FPGA, the hexadecimal value of the data received from the pc plus 1 and then sent to a PC design microcontroller and FPGA interface module, the received data sent to the MCU, and displayed on the LCD
Platform: | Size: 427008 | Author: katheqiu | Hits:

[VHDL-FPGA-Verilog] VHDL_LCDPUART_example10

Description: VHDL实现的串口通讯和1602液晶显示的实验程序，可以从PC发送数据到FPGA，并在LCD上显示，也可从FPGA开发板上键入数据，在LCD上显示，并通过串口发送到PC机上，适合初学者入门使用，-VHDL realization of the experimental program of serial communication and 1602 LCD, you can send the data from the PC to the FPGA, and displayed on the LCD, data from FPGA development board type is displayed on the LCD, and sent to the PC via the serial port, Suitable for beginner to use,
Platform: | Size: 2179072 | Author: linbaoluo | Hits:

[Com Port] test1_rx

Description: fpga实现串口数据通信，实现PC与目标设备通信-fpga control uart
Platform: | Size: 513024 | Author: yangsheng | Hits:

[VHDL-FPGA-Verilog] VHDL_uart

Description: 用xilinx的FPGA-spartan3E实现uart，固定波特率9600，偶校验，系统时钟50MHz，能够实现将从串口调试助手发送到FPGA的数据重新发回串口调试助手-using xilinx s FPGA-spartan3E to implement uart with a baudrate of 9600, even parity check. The system frequency is 50MHz.It can turn the data from serial assistant in PC back to the PC
Platform: | Size: 731136 | Author: john | Hits:

[VHDL-FPGA-Verilog] yibuchuanxingjiekou

Description: 能进行异步全双工串行通信的模块，该模块以固定的串行数据传送格式收发数据。每帧数据共10 位，其中1 位启动位，8 位数据位，1 位停止位。模块发送的数据由PC 端的串口调试助手接收，要求能发送数字和中文（一首古诗，在FPGA内采用ROM 的方式存储中文内码），并能进行切换。模块接收PC 端串口调试助手发送的16 进制数据，可按10 进制方式显示到LED 上。-Asynchronous full-duplex serial communications module can be performed, the data of the module to the fixed serial data transmission format transceiver. 10 of each frame of data, a start bit, 8 data bits, 1 stop bit. Module sends the data received from the PC side of serial debugging assistant requirements can send digital and Chinese (a poem using the FPGA code ROM stored in a manner Chinese), and can be switched. The module receives the PC side of serial debugging assistant send hexadecimal data can be decimal display on the LED.
Platform: | Size: 2847744 | Author: 王婷 | Hits:
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